From Jan Van der Spiegel - Center for Sensor Technologies
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Dr. Van der Spiegel's research interests are in analog and digital integrated circuits for intelligent sensors, data converters, data acquisition and sensory data processing systems. His sensor work focuses on new approaches to vision sensors that are able to detect certain features such as motion, line orientation, line stops, and polarization difference. He has also worked on acoustic-phonetic feature extraction for automatic speech recognition, and spectral conversion for Speech Enhancement. A related aspect of Dr. Van der Spiegel's research is low-power, low-voltage and low-noise integrated circuits for sensors and data acquisition systems.

Brain Machine Interface

(with Nader Engheta, Timothy H. Lucas, Andrew G. Richardson, Milin Zhang, Xilin Liu, Hongjie Zhu)

  • Project description

A Brain Machine Interface (BMI) creates artificial pathway between the brain and external hardware, which has shown promise in replacing sensory and motor pathways lost due to neurological injury or disease. This program explores device implementation, signal processing, as well as custom circuit design.

  • Related publication
  1. X. Liu, M. Zhang, J. Van der Spiegel, "Design of a High Efficiency, Net-Zero Charge Neural Stimulator with Arbitrary Channel Configuration", IEEE Biomedical Circuits and Systems Conference (BioCAS), pp 492-495, 2014.
  2. X. Liu, B. Subei, M. Zhang*, A. Richardson, T. Lucas, J. Van der Spiegel, "The PennBMBI: a General Purpose Wireless Brain-Machine-Brain Interface System in Unrestrained Animals", IEEE International Symposium on Circuits and Systems (ISCAS), 2014.
  3. X. Liu, M. Zhang, A. Richardson, T. Lucas, J. Van der Spiegel, "Design of a General Purpose Wireless Brain-Machine-Brain Interface System", IEEE Transaction on Biomedical Circuits and Systems, 2014
  4. X. Liu, H. Zhu, M. Zhang, A. G. Richardson, T. H. Lucas, J. Van der Spiegel, “Design of a Low-Noise, High Power Efficiency Neural Recording Front-end with an Integrated Real-Time Compressed Sensing Unit”, IEEE International Symposium on Circuits and Systems (ISCAS), 2015 (Accepted)
  5. H. Zhu, M. Zhang, A. G. Richardson, T. H. Lucas, J. Van der Spiegel, “Design of a Low Power Impulse-Radio Ultra-Wide Band Wireless Electrogoniometers”, IEEE International Symposium on Circuits and Systems (ISCAS), 2015 (Accepted)

  • Potential research opportunity
1. Design of a smart sensor networks for primate training
[show details]
2. Design of Wearable Human Gesture Recognition System
[show details]

Sensor technologies

This program deals with the study and development of systems that are able to deal with complex sensory processing tasks, such as vision and speech. The approach followed is to a large extent inspired by the biological system and makes use of a hierarchy of processing stages. The overall system consists of dedicated sensors embedded with local processing elements, followed by a neural network that performs higher levels of processing.

Polarization Image Sensor

(with Prof. Nader Engheta, Ed Pugh, Viktor Gruev, Milin Zhang and Xiaotie Wu)

Imager merged with polymer micro polarization array

  • Project description

We are working on a imaging system for the extraction of polarization information. This work consists of two part. The first aspect focuses on a CMOS based imager that is capable of real-time extraction of polarization information. The imaging system consists of a photo array of active pixels, an analog processing unit at the focal plane for noise suppression and computation of the Stokes parameters. The second aspect deals with the development of a micropolarizer thin film.

  • Related publication
  1. V. Gruev, J. Van der Spiegel and N. Engheta, "Image Sensor With Focal Plane Extraction of Polarimetric Information," Proc. of the Proc. IEEE ISCAS, May 2006.
  2. V. Gruev, A. Ortu, N. Lazarus, J. Van der Spiegel, and N. Engheta, "Fabrication of a dual-tier thin film micropolarization array," Optics express, vol. 15, no. 8, pp. 4994-5007, Apr. 2007.
  3. V. Gruev, J. Van der Spiegel, and N. Engheta, "Advances in integrated polarization image sensors," Proc. of IEEE/NIH Life Science Systems and Applications Workshop, pp. 62-65, Apr. 2009.
  4. V. Gruev, J. Van der Spiegel, and N. Engheta, "Dual-tier thin film polymer polarization imaging sensor.," Optics express, vol. 18, no. 18, pp. 19292-303, Aug. 2010.
  5. M. Zhang, K. Ihida-Stansbury, J. Van der Spiegel, and N. Engheta “Polarization-based non-staining cell detection”, Optics Express, vol. 20, no. 23, pp. 25378-25390, 2012.
  6. M. Zhang, X. Wu, N. Engheta, J. Van der Spiegel, "A Monolithic CMOS Image Sensor with Wire-Grid Polarizer Filter Mosaic in the Focal Plane", IEEE Transactions on Electron Devices (TED), vol. 61. no. 3, pp. 855-862, 2014.
  7. M. Zhang, X. Wu, N. Cui, N. Engheta, J. Van der Spiegel, “Bio-Inspired Focal-Plane Polarization Image Sensor Design: From Application to Implementation”, Proceedings of the IEEE, vol. 102, no. 10, pp. 1435-1449, 2014

Current Mode Imager Sensor

(with Zheng Yang, Viktor Gruev, Xiaotie Wu, Milin Zhang)

  • Project description

We are also studying new approaches for CMOS imagers. We are developing a CMOS image sensor that is capable of both voltage- and current-mode operations. We have also proposed a novel current-mode readout technique using a velocity saturated short-channel transistor, which achieves high linearity. We are also developing new pixels structures and read-out schemes that allow us to reduce the number of transistor per pixels.

  • Related publication
  1. Zheng Yang, Viktor Gruev and Jan Van der Spiegel, "A CMOS Linear Voltage/Current Dual-Mode Imager," Proc. of the IEEE ISCAS, May 2006。
  2. V. Gruev, Z. Yang, J. Van der Spiegel, and R. Etienne-Cummings, “Two Transistor Current Mode Active Pixel Sensor,” Proc. of ISCAS, International Symposium on Circuits and Systems, pp. 2846-2849, May. 2007.
  3. R. M. Philipp, D. Orr, V. Gruev, J. Van der Spiegel, and R. Etienne-Cummings, “Linear Current-Mode Active Pixel Sensor,” IEEE Journal of Solid-State Circuits, vol. 42, no. 11, pp. 2482-2491, Nov. 2007.
  4. V. Gruev and J. Van der Spiegel, Current-mode image sensor with 1.5 transistors per pixel and improved dynamic range. IEEE, 2008, pp. 1850-1853.
  5. V. Gruev, Z. Yang, and J. Van der Spiegel, “Low-power reduced transistor image sensor,” Electronics Letters, vol. 45, no. 15, p. 780, 2009.
  6. V. Gruev, Z. Yang, J. Van der Spiegel, and R. Etienne-Cummings, “Current Mode Image Sensor With Two Transistors per Pixel,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 6, pp. 1154-1165, Jun. 2010.
  7. X. Wu, X. Liu, M. Zhang*, J. Van der Spiegel, "Current Mode Image Sensor with Improved Linearity and Fixed-Pattern Noise", IEEE Transactions on Circuits and Systems I (TCAS-I), vol. 61, no. 6, pp. 1666-1674, 2014.

Feature Detection

(with Masatoshi Nishimura)

Sensor responses to various letter images

  • Project description

We have been working on a vision sensor that serves as an intelligent front end of a pattern recognition system. The sensor detects higher level image features, such as corners, junctions (T-, X-, Y-type) and linestops. The on-chip detection of these features significantly reduces the data amount and hence facilitates the subsequent processing of pattern recognition. The sensor performs a series of template matching operations in an analog/digital mixed mode for various kinds of image filtering operations including thinning, orientation decomposition, error correction, set operations, and others. The analog operations are done in the current domain. These features serve as input to a system that recognizes characters or categorizes objects in broad categories. The pixels are programmable and consist of photodetectors and circuitry that can be configured to perform a variety of spatial filtering operations.

  • Related publication
  1. "Biologically Inspired Vision Sensor for the Detection of Higher-Level Image Features," M. Nishimura and J. Van der Spiegel, Proceedings of the 2003 IEEE Conference on Electron Devices and Solid-State Circuits, pages 11-16, 2003
  2. "A CMOS Image Processing Sensor for the Detection of Image Features,” Journal Analog Integrated Circuits and Signal Processing, Vol. 43, pp. 1-17, 2005, M. Nishimura and J. Van der Spiegel.
  3. "An algorithm for the detection of image features on a smart sensor," Technical Report, M. Nishimura and J. Van der Spiegel, 2003.
  4. "A VLSI Computational Sensor for the Detection of Image Features,' Masatoshi Nishimura, Ph.D. Thesis, Dept. Electrical Engineering, Univ. of Pennsylvania, Philadelphia, PA

Tracking Sensor

(with Dr. Ralph Etienne-Cummings and P. Mueller, Corticon Inc.)

Microphotograph of the Tracking Chip. (6.4x6.8 mm2 / 2 um CMOS)

  • Project description

We developed a motion perception chip which acquires a two-dimensional images and determines the direction of motion. The chip's architecture and processing elements are biologically motivated. The chip makes use of a spatially variant sampling structure and of an arbitration scheme between smooth pursuit and acquisition to improve the tracking process.

A foveal region contains edge detection, contrast normalization circuits and computes divergent 2D velocity. The peripheral region is used to re-capture targets which escape the fovea. The system is used for object tracking. The center area contains the foveal pixels used for directional motion while the peripheral area is used for target location.

  • Related publication
  1. "A Foveated Visual Tracking Chip", Technical Digest, Intern. Solid-State Circuits Conference (ISSCC97), pp. 38-39, 1997 (pdf file - 240 kB)"
  2. "A Foveated Silicon Retina for Two-Dimensional Tracking", IEEE Trans. Circuits and Systems II, Vol. 47, pp. 504-517, June 2000; R. Etienne-Cummings, J. Van der Spiegel, P. Mueller and M.Z. Zhang.
  3. "A Motion Perception and Visual Tracking Chip," Penn Technology News, Vol 5, Fall 1998.

Retina-like Imager

(with Dr. Greg Kreider)

Micrograph of the Retina Sensor Chip
  • Project description

Van der Spiegel and his group developed a foveated retina-like CCD sensor in collaboration with Prof. C. Claeys at IMEC, Prof. G. Sandini at the University of Genova, and Prof. P. Dario at the Scuola Superiore S. Anna, Pisa. This device is an example of a sensor whose computational properties are embedded in the geometry of the structure. This sensor explores the log-polar sampling space and provides significant functional and computational advantages over conventional imagers for real-world vision tasks. The sensor incorporates several unique structures and makes use of the capabilities of CCD technology to implement both optical and electronic functions.

  • Related publication
  1. "A Retinal CCD Sensor for Fast 2D Shape, Recognition and Tracking," Sensors and Actuators, Vol. A21, pp. 456-460, 1990. I. Debusschere, E. Bronckaers, C. Claeys, G. Kreider, J. Van der Spiegel, G. Sandini, P. Dario, F. Fantini, P. Bellutti, G. Soncini
  2. "A Foveated Retina-Like Sensor Based on CCD Technology," in "Analog VLSI Implementation of Neural Systems", eds. C. Mead and M. Ismail, Kluwer Academic Publ., Boston, MA, 1989, Chapter 8, pp. 189-210; also in Vision Chips: Implementing Vision Algorithms with Analog VLSI Circuits, pp. 442-465, IEEE Press (Selected Reprint Volume), by C. Koch and H. Li, 1995.J. Van der Spiegel, G. Kreider, C. Claeys, I. Debusschere, G. Sandini, P. Dario, F. Fantini, P. Bellutti and G. Soncini.

Related work to Space Variant Sensors: Univ. of Genoa - Lira Lab

General Purpose Neural Computer

(with Dr. Paul Mueller, Corticon Inc., D. Blackman, C. Donham, R. Etienne-Cummings)

Micrograph of a test chip containing 5 neurons

  • Project description

Our group developed in collaboration with Corticon Inc. a large scale programmable analog neural computer. The architecture is loosely modeled after the pathways in the human brain.. The network consists of over 800 custom VLSI modules and contains programmable neurons, synapses, synaptic time constants and programmable interconnects. The computer runs in analog mode which enables a truly simultaneous summation of many inputs at a single neuron while the programmable time constants permit dynamic computation of temporal patterns as they occur in motion and speech.

The machine is intended for real-time, real world computations such as speed recognition, sonar, ultrasonic, vision, robotics, control automation and other applications requiring computational power and speed exceeding the performance limit of current digital machines. One of the most promising applications is speaker independent speech recognition. The neural network decomposes speech in a sparse set a pattern primitives that will be used to recognize phonemes. Phoneme-based recognition systems are simpler than word-based systems and have the potential to be speaker independent and requires less hardware to be implemented.

  • Related publication
  1. P. Mueller, J. Van der Spiegel, D. Blackman, T. Chiu, T. Clare, J. Dao, C. Donham, T. Hsieh, M. Loinaz, "A general purpose analog neural computer," International Joint Conference on Neural Networks, 1989. IJCNN., vol.2 pp.177-182, 1989.
  2. J. Van der Spiegel, D. Blackman, P. Chance, C. Donham, R. Etienne-Cummings and P. Kinget, "An Analog Neural Network with Modular Architecture for Real-Time Dynamic Computations," in IEEE J. Solid-State Circuits, Vol. 27, pp.82-92, 1992.
  3. P. Mueller, J. Van der Spiegel, D. Blackman, T. Chiu, T. Clare, J. Dao, C. Donham, T-P. Hsieh and M. Loinaz, "A Programmable Analog Neural Computer and Simulator," in Artificial Neural Networks, E. Sanchez-Sinencio and C. Lau, Eds., IEEE Press (Selected Reprint Volume), pp. 218-224, 1992.
  4. P. Mueller, J. Van der Spiegel, D. Blackman, C. Donham and R. Etienne-Cummings, "Real Time Decomposition of Acoustical Patterns with an Analog Neural Computer," SPIE Conf. on Applications of Artificial Neural Networks III, Vol. 1709, pp. 758-769, 1992.

Analog circuit design

Background Calibration of A/D Converters

(with Sameer Sonkusale, Alper Meric)

Micrograph of the background calibration of A/D converters

  • Project description

A/D converters suffer from several non-idealities like INL, DNL, offset,harmonic distortion due to capacitor mismatches, finite gain of the opamp, offsets in the comparator, parasitics and several other phenomenon related to a particular architecture. Techniques to increase the resolution of an A/D converter have so far been in terms of self-calibration of the A/D converter, which requires the A/D converter to stop conversion every few cycles to perform calibration. Techniques have to be designed such that calibration can be performed in background without stopping conversion.The scope of this research involves identifying and modeling the non-idealities in an A/D converter efficiently and to develop a speed-power efficient architecture and algorithm to perform calibration in the background.

We are investigating several calibration methods. One such background calibration method is based on stage error pattern estimation The method corrects both linear and non-linear errors. The procedure converges in a few ms and requires minimal hardware without the need of highcapacity ROM or RAM.

  • Related publications
  1. "Background Digital Error Correction Technique for Pipelined Analog-Digiital Converters", IEEE International Symposium on Circuits and Systems 2001 (ISCAS 2001) Volume 1, pages 408-411, S. Sonkusale, J. Van der Spiegel, and K. Nagaraj.
  2. "True Background Calibration Technique for Pipelined ACD", Electronics Letters, Vol. 36, No. 9, pp786-788, 2000, S. Sonkusale, J. Van der Spiegel, and K. Nagaraj."
  3. "Mixed-Signal Calibration of Pipelined Analog-Digital Converters," Proceedings of the 2003 IEEE International SOC [Systems-on-Chip] Conference, pages 327-330, S. Sonkusale and J. Van der Spiegel.
  4. "A Low Distortion MOS Sampling Circuit," Proceedings of the IEEE International Symposium on Circuits and Systems 2002 (ISCAS 2002), Volume 5, pages V-585 - V-588; S. Sonkusale and J. Van der Spiegel
  5. "A 50MS/s 12-bit CMOS Pipeline A/D Converter with Nonlinear Background Calibration,” IEEE Custom Integrated Circuit Conference (CICC 2005), Sept. 2005, Jie Yuan, N. Farhat and J. Van der Spiegel.
  6. "GBOPCAD: A Synthesis Tool for High-Performance Gain-Boosted Opamp Design," IEEE Transactions on Circuits and Systems--I: Regular Papers, Volume 52, Issue 8, August 2005, pages 1535-1544, Jie Yuan, N. Farhat and J. Van der Spiegel.

Modeling of Power Dissipation in Δ-Σ converters

(with Qunying Li and Dr. Ken Laker)

  • Project description

This project involves the development of architectures that enable a delta-sigma ADC to realize high dynamic range requirements when implemented in low-voltage technologies and to minimize overall power dissipation. In order to be able to compare different schemes a "Energy-per-Conversion" (EPC) model was developed. The purpose of the EPC model is to provide a figure of merit that enables one to understand the trade-offs that exist in low-voltage, low-power delta-sigma converter design. The model starts with the fundamental lower bound based on thermal noise considerations of the input stage and gives a relationship between the energy-per-conversion and signal-to-noise ratio (SNR).

Signal Adaptive Control Architecture for a Δ-Σ converter

(with Qunying Li, Dr. Ken Laker))

  • Project description

We have been working on a Signal Adaptive Control (SAC) architecture for a 2nd order delta-sigma modulator. This scheme reduces the power dissipation and the harmonic distortion in the first stage integrator. The key to the operation is the switching off of the DAC feedback signal to the 1st stage during certain iterations and to compensate the signal at the input of the 2nd stage in an adaptive manner.

  • Related publications
  1. "A Low-Voltage/Low-Power Second-Order Delta-Sigma Modulator with Signal Adaptive Control Architecture," IEEE ISCAS, May, 1999, Proc. Vol. II, pp. 41-44 (pdf file - 190kB)"Signal Adaptive Control Architecture of Delta-Sigma Modulator Design", Electronics Letters, Vol. 35, No. 8, p. 610, 1999"
  2. "A 1.2 V, 38 microW Second-Order DeltaSigma Modulator with Signal Adaptive Control Architecture ," IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits and Systems 2001 (DCAS 2001), pages P23-P26, Qunying Li, K. Laker and J. Van der Spiegel
  3. "An Overview of Sigma-Delta Converters: How a 1-bit ADC achieves more than 16-bit resolution," Signal Processing Magazine, Volume 13, Issue 1, September 1996, pages 61-84, A. M. Pervez, H. V. Sorensen, J. Van der Spiegel.

Phase-Locked Loop

(with Chao Xu, Ken Laker and Winslow Sargeant)

Micrograph of PLL (345x803um2)

  • Project description

A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology has been studied and developed.. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency.

  • Related publications
  1. "A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter," Analog Integrated Circuits and Signal Processing, Volume 36, Issue 1-2, July 2003, pages 91-97, Chao Xu, W. Sargeant, K. Laker and J. Van der Spiegel.
  2. " An Extended Frequency Range CMOS Voltage-Controlled Oscillator," Proceedings of the 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002), Volume 2, pages 425-428, Chao Xu, W. Sargeant, K. Laker and J. Van der Spiegel.

Signal processing

Spectral Conversion for Speech Enhancement

(with Dr. A. Mouchtaris, P. Mueller and A. Ali)

Current voice conversion algorithms require a parallel speech corpus that contains the same utterances from the source and target speakers for deriving a conversion function. We have worked on a voice conversion method that does not require a parallel corpus for training, i.e. the spoken utterances by the two speakers need not be the same, by employing speaker adaptation techniques to adapt to a particular pair of source and target speakers, the derived conversion parameters from a different pair of speakers. We have shown that adaptation reduces the error obtained when simply applying the conversion parameters of one pair of speakers to another by a factor that can reach 30% in many cases, and with performance comparable with the ideal case when a parallel corpus is available.

We have also demonstrated that spectral conversion can be successfully applied to the speech enhancement problem as a feature denoising method. The enhanced spectral features can be used in the context of the Kalman filter for estimating the clean speech signal. In essence, instead of estimating the clean speech features and the clean speech signal using the iterative Kalman filter, we show that is more efficient to initially estimate the clean speech features from the noisy speech features using spectral conversion (using a training speech corpus) and then apply the standard Kalman filter. Our results show an average improvement compared to the iterative Kalman filter that can reach 6 dB in the average segmental output Signal-to-Noise Ratio (SNR), in low input SNR’s.

Acoustic-Phonetic Feature Extraction

(with Prof. P. Mueller and Ahmed A. Ali )

Over the last several years we have also investigated methods to improve speech recognition. Our goal is to integrate acoustic-phonetic knowledge into speech recognition systems. A novel strategy is used for this purpose. We use auditory-based front-end preprocessing that incorporates many of the human-like effects such as critical band filtering, short-term adaptation forward masking, non-linearities, etc. The output of such a preprocessing block feeds into a system that extracts acoustic-phonetic features. The extracted features are chosen based on their information content and discrimination ability in various tasks. Algorithms are designed and implemented for phoneme recognition. We have applied this method successfully for speech segmentation, fricative and stop recognition.

Materials for Microelectronics

Ternary systems for VLSI microelectronics

(with Michael Setton)

Group VIII metals such as Fe, Co, Ni, Pd and Pt form stable ternary phases with other transition metals. This tendency is explained using an empirical approach where parameters affecting phase formation and solubility are electron affinity, atomic radii and valency. Metal-dopant compound formation is also reviewed for Metal-Boron-Si systems. Following the literature review, the validity of other models is discussed.

Experimentally, thin film growth of Ti4Ni4Si7, Ti0.75Co0.25Si2, TiCoSi, Ti4Co4Si7 and ZrCuSi2 is observed for the first time. Crystallographic structures and electrical properties of selected compounds are presented. Samples are prepared by Rapid Thermal Processing (RTP) in vacuum. RTP is shown to be also advantageous to form smooth low resistivity silicides such as TiSi2, CoSi2 (15-18 μΩ.cm) and ZrSi2 (34 μΩ.cm).

Structure and transport of epitaxial rare earth silicides

(with Dr. William R Graham, and Forrest H. Kaatz)

A multi-technique investigation of the growth, structure, and transport behavior in two epitaxial rare earth silicides: erbium silicide, ErSi2-x, and terbium silicide, TbSi2-x, has been conducted. The rare earth silicides form in a planar hexagonal AlB2 structure with a good lattice match to the Si(111) surface. This is the first time these materials have been formed under ultra high vacuum conditions, allowing the characterization of the structure and transport behavior of the heteroepitaxial systems.

Senior Designs

Year Group members Project
2013-2014 Raphael Benarrosh, ShahaabBhanji, Christian Collins,PouriaSanjari Wearable Active Tactile Sensory System (WATSS) [show details]
2012-2013 Eric J He, Daniel H Wiegard, Adish D Mohnot, David J Robinson The Smarter Train [show details]
2012-2013 Jessica Jiang, Taylor Lee, Connie Wu HearSight [show details]
2012-2013 Cameron Cogan, David Hallac, Nicholas Howarth, Ashleigh Thomas, Samuel Wolfson Primate Hand Actuation Tracker (PHAT) [show details]
2012-2013 Tedd Ahn, Alex Hildick-Smith, Rick Krajewski, Rick Krajewski Wireless Neural Recording System [show details]
2012-2013 Jonatha Post, Alec Miller, Elizabeth Rubenfield, Nora Turek ExtensionEvaluator [show details]
2011-2012 Akhilesh A Nayak, Eric L Chen, Benjamin K Shyong High-speed, High-precision A2D Interface for Flexible, Active Electrode Arrays [show details]
2011-2012 Aditya V Jayanthi, Madhav M Nandipati, Khaled Saad, Arshan B Vakil Penn Schedule Assembler [show details]
2011-2012 Akhilesh A Nayak, Eric L Chen, Benjamin K Shyong High-speed, High-precision A2D Interface for Flexible, Active Electrode Arrays [show details]
2009-2010 Ross Kessler, Stewart Laird, Anthony Mattei and Vadim Svirskiy System for Detection and Analysis of Hospital Ward Noise Sources [show details]
2008-2009 Tim McKenna, Anil Venkatesh, Neeraj Wahi, Nicholas Annetta Iris: Vision Beyond Obstructions [show details]
2007-2008 Anujit Shastri, Darren Wang Polarizing Processing for Low Light Imaging [show details]
2007-2008 Michael Costa, Alexis Wong Pitcher Performance Tracker [show details]
2006-2007 Lucy Zhang, Shranya Srinivasan, Nathan Lazarus Motion Tracking Camera [show details]
2005-2006 Lee Becker, Kanush Choudhary, Tejsvi Rai Low Power Wireless Security Network [show details]
2005-2006 Ann Chempakaseril, Faizah Ramlee Programmable Photoresist Spinner [show details]
2005-2006 Mark Dweck, Louie Huang, Dan Koch Generic USB 2.0 Custom Video Sensor Platform [show details]
2005-2006 Zhan Chen, Albert Ip, Kejia Wu IntelliCam: An Intelligent Visual Tracking System [show details]
2004-2005 Seth Charlip-Blumlein, Shehzad Khan Engineering a Better Golf Swing [show details]
2004-2005 Navajeet Chatterji, Sunava Dutta Voice Activated Search Engine [show details]
2003-2004 Giridhar Nandipata, Aunim Hossain Ultrasonic Position Sensing for Location-aware Applications
2003-2004 Brian Falk, Jennifer Hall ENIAC on an FPGA
2003-2004 Albert Kim, Fred Li ENIAC on an FPGA
2003-2004 Arthur Cao Yuan Artificial Cochlea
2002-2003 Aamer Ghouse, Aditya Talwar, Henry Tam FPGA Implementation of Artificial Human Cochlea Front End FPGA Implementation of an Artificial Human Cochlea [show details]
2002-2003 Kunal Ghosh, King Yeung CMOS Camera-On-Chip with Polarization Difference Imaging [show details]



Dr. Van der Spiegel is coordinating the REU Summer Undergraduate Research for Undergraduates (SUNFEST) program which provides summer research position for motivated undergraduate students. The area of research is in Sensor Technologies and includes physical sensors, chemical sensors, neural networks, electronic materials, nanotechnology and robotics. Typically 10 students participate per summer.


Year Name Home Univ. Project
2014 Antonio Basukoski Columbia Univ. Second-Order Hilbert Curve Scattering Antennas to a Farfield EM Source [show details]
2013 Basheer Subei UIUC Microcontroller-based General Platform for a Wireless Brain-Computer Interface [show details]
2012 Carlos Biaou Prince George's Community College Programmable Time Division Multiple Polarization Graphic [show details]
2006 Nathan Lazarus UPenn Fabrication of PVA Micropolarizer Arrays for CMOS Image Sensor [show details]
2006 William Peeples Lincoln Univ. Testing of a Novel Custom Made CMOS Imaging Sensor [show details]
2005 Kejia Wu UPenn Fabrication of micro-polarizer array with polymer thin film [show details]
2003 Emily R. Blem Swarthmore College Implementation of the eniac accumlator and cycling unit on a field programmable gate array [show details]
2002 Aslan Ettehadieh Morgan St. Univ. Design of an artificial cochlea using digital filters on a field-programmable gate array [show details]
2001 Gregory J. Barlow North Carolina St.Univ Active pixel sensor for a polarization-difference camera [show details]
2001 EunSik Kim UPenn Neural network with application to real time phoneme recognition [show details]
2000 DeAnna Burns UPenn Fabrication of a cell-based biosensor using green tape ceramics with human embryonic kidney and sea urchin egg cells [show details]
2000 Shiva Portonovo UPenn Components of a cmos imager for a polarization-difference camera [show details]
1999 David Auerbach Swarthmore Stop consonant classifiction using recurrant neural networks [show details]
1999 Patrick Lu Princeton Univ IdentifyingKey Phoneme Features in Spectrograms [show details]
1998 Jeffrey Berman UPenn Recognition of semivowels and nasals in continuous speech[show details]
1998 David Friedman UPenn Real-time vowel recognition using a neural computer[show details]
1998 Sancho Pinto UPenn Isolated word recognition using hidden markov models[show details]
1997 Gavin Haentjes UPenn Speech synthesis from a spectrogram[show details]
1997 Ali Husain UPenn A Microlens Array To Increase The Fill Factor Of A Cmos Camera [show details]
1997 Joseph Murray Univ of Oklahoma Implementing Learning Algorithms For Pattern Recognition On A Neurocomputer[show details]
1997 O'Neil Palmer UPenn SAM: A Graphical User Interface For The Analysis And Manipulation Of Spectrograms[show details]
1997 Kelum Pinnaduwage UPenn SAM: A Graphical User Interface For The Analysis And Manipulation Of Spectrograms[show details]
1995 Tyson S. Clark Utah St. Univ. Real-Time Speech Recognition Using A Neural Computer[show details]
1995 Brandeis Marquett JHU Real-Time Tracking And Target Acquisition With Silicon Retina And Pc[show details]
1995 Benjamin A. Santos Univ. of Puerto Rico-Mayaguez E.N.I.A.C. Hardware Implementation[show details]
1994 Alyssa Apsel Swarthmore College Spatio-Temporal Velocity Detection In Two Dimensions With A Neural Network And A Silicon Retina[show details]
1994 Paul Longo UPenn Real Time Velocity-Based Target Tracking With Silicon Retina And Pc[show details]